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Silterra
Silterra 0.11um CMOS Logic Generic
CMOS Logic

CL110G

SilTerra’s CL110G is a 10% optical shrink version from generic CL130G process.
The electrical performance and design rules of device will be remained as CL130G before
tapeout but the technology will enable more gross die per wafer which provides a natural cost 
reduction plan for our customers. 
 
CL110G Key Process Features 
   Industry standard 0.13µm CMOS logic technology
   Multiple voltages: 1.2V core, 2.5V/3.3V I/O
   Single-poly, up to eight metal layers
   FSG inter-metal dielectric
   High Vt option available
   Dual damascene copper metalization
   RO delay: 20ps/stage (Nominal Vt)
   Gate density: 230KG/mm2
   SRAM cell: 2.43µm2 and 2.14µm2


Physical Design Rule



Electrical Design Rule (Specification) 

Silterra 0.13um CMOS Logic Generic
CMOS Logic

CL130G

SilTerra’s CL130G technology (0.13um CMOS Logic Generic) is process matched to leading foundry. The all-copper process features borderless contacts and vias and up to eight layers of metal. This technology offers high speed and high gate density performance which is suitable for design in high speed digital consumer, wired communication and computation related applications. 

Our CL130HVt technology (0.13um CMOS Logic High Vt) features the optimum transistor performance between speed and standby power. This process technology targets high speed portable devices.

Both CL130G and CL130HVt technologies are supported by silicon verified standard design libraries, SRAM compilers, I.O. Libraries and IPs. 
 
CL130G Key Process Features 
   Industry standard 0.13µm CMOS logic technology
   Multiple voltages: 1.2V core, 2.5V/3.3V I/O
   Single-poly, up to eight metal layers
   FSG inter-metal dielectric
   High Vt option available
   Dual damascene copper metalization
   RO delay: 20ps/stage (Nominal Vt)
   Gate density: 230KG/mm2
   SRAM cell: 2.43µm2 and 2.14µm2


Physical Design Rule



Electrical Design Rule (Specification) 

Silterra 0.18um CMOS Logic Generic
CMOS Logic

CL180G

SilTerra’s CL180G (0.18um CMOS Logic Generic) baseline technology is in high volume production with excellent yield. This technology is process matched to foundry standard and positioned for main-stream digital consumer & communication related applications. 

The technology offer the best combination of density, speed and power which are supported by a complete set of silicon proven standard design libraries, SRAM compiler, I/O and IP’s.
 

 

 

CL180G Key Process Features 
   Single-poly and up to six metal layers
   Dual gate: 1.8V core and 3.3V I/O
   Cobalt silicided source, drain and gate
   Shallow trench isolation
   Aluminum metallization with tungsten plug
   FSG inter-metal dielectric
   Metal-Insulator-Metal (MIM) Capacitor (Option)
   SRAM bit cell: 4.65µm2


Physical Design Rule



Electrical Design Rule (Specification) 

Silterra 0.13um RFCMOS
Mixed Signal / RF

CL130MR

Silterra’s CL130MR (0.13um RFCMOS) is developed specifically for wireless applications in WLAN a/b/g,Bluetooth, RF transceiver & tuners. Many RF circuits are already proven in our RFCMOS technology. 
This technology is supported with complete RF models and RF design kits that are silicon proven.
 
CL130MR Key Process Features 
   Single-poly and up to six metal layers
   Supports 1.8V and 3.3V power supplies
   Shallow trench isolation 
   Dual gate oxide
   Surface channel NMOS and PMOS 
   Cobalt silicided source, drain and gate
   Borderless contact and vias
   High density plasma gap fill
   FSG inter-metal dielectric
   Native transistors
   Metal-Insulator-Metal Capacitor ( 1fF/µm2 or 2fF/µm2 )
   Thick metal spiral inductor
   Varactor Metal Finger Capacitor ( 1.30 fF/µm2 )
   Thick Metal Spiral Inductor ( 2.3µm )
   Ft NMOS ( 56.2 GHz )


CL130MR Device Performance 

Silterra 0.18um RFCMOS
Mixed Signal / RF

CL180MR

Silterra’s CL180MR (0.18um RFCMOS) is developed specifically for wireless applications in WLAN a/b/g,Bluetooth, RF transceiver & tuners. Many RF circuits and models already proven in our RFCMOS technology. This technology is supported a complete RF models and RF design kits with silicon proven.
 
CL180MR Key Process Features 
   Single-poly and up to six metal layers
   Supports 1.8V and 3.3V power supplies
   Shallow trench isolation 
   Dual gate oxide
   Surface channel NMOS and PMOS 
   Cobalt silicided source, drain and gate
   Borderless contact and vias
   High density plasma gap fill
   FSG inter-metal dielectric
   Native transistors
   Metal-Insulator-Metal Capacitor ( 1fF/µm2 or 2fF/µm2 )
   Thick metal spiral inductor
   Varactor Metal Finger Capacitor ( 1.30 fF/µm2 )
   Thick Metal Spiral Inductor ( 2.3µm )
   Ft NMOS ( 56.2 GHz )


Physical Design Rule



Electrical Design Rule (Specification) 

 

 

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