| Silterra 0.11um CMOS Logic Generic |
| CMOS Logic |
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CL110G
SilTerra’s CL110G is a 10% optical shrink version from generic CL130G process.
The electrical performance and design rules of device will be remained as CL130G before
tapeout but the technology will enable more gross die per wafer which provides a natural cost
reduction plan for our customers.
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| CL110G Key Process Features |
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Industry standard 0.13µm CMOS logic technology |
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Multiple voltages: 1.2V core, 2.5V/3.3V I/O |
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Single-poly, up to eight metal layers |
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FSG inter-metal dielectric |
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High Vt option available |
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Dual damascene copper metalization |
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RO delay: 20ps/stage (Nominal Vt) |
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Gate density: 230KG/mm2 |
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SRAM cell: 2.43µm2 and 2.14µm2 | |
Physical Design Rule
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Electrical Design Rule (Specification)
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| Silterra 0.13um CMOS Logic Generic |
| CMOS Logic |
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CL130G
SilTerra’s CL130G technology (0.13um CMOS Logic Generic) is process matched to leading foundry. The all-copper process features borderless contacts and vias and up to eight layers of metal. This technology offers high speed and high gate density performance which is suitable for design in high speed digital consumer, wired communication and computation related applications.
Our CL130HVt technology (0.13um CMOS Logic High Vt) features the optimum transistor performance between speed and standby power. This process technology targets high speed portable devices.
Both CL130G and CL130HVt technologies are supported by silicon verified standard design libraries, SRAM compilers, I.O. Libraries and IPs.
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| CL130G Key Process Features |
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Industry standard 0.13µm CMOS logic technology |
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Multiple voltages: 1.2V core, 2.5V/3.3V I/O |
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Single-poly, up to eight metal layers |
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FSG inter-metal dielectric |
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High Vt option available |
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Dual damascene copper metalization |
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RO delay: 20ps/stage (Nominal Vt) |
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Gate density: 230KG/mm2 |
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SRAM cell: 2.43µm2 and 2.14µm2 | |
Physical Design Rule
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Electrical Design Rule (Specification)
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| Silterra 0.18um CMOS Logic Generic |
| CMOS Logic |
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CL180G
SilTerra’s CL180G (0.18um CMOS Logic Generic) baseline technology is in high volume production with excellent yield. This technology is process matched to foundry standard and positioned for main-stream digital consumer & communication related applications.
The technology offer the best combination of density, speed and power which are supported by a complete set of silicon proven standard design libraries, SRAM compiler, I/O and IP’s.
Physical Design Rule
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Electrical Design Rule (Specification)
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| Mixed Signal / RF |
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CL180MR
Silterra’s CL180MR (0.18um RFCMOS) is developed specifically for wireless applications in WLAN a/b/g,Bluetooth, RF transceiver & tuners. Many RF circuits and models already proven in our RFCMOS technology. This technology is supported a complete RF models and RF design kits with silicon proven.
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| CL180MR Key Process Features |
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Single-poly and up to six metal layers |
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Supports 1.8V and 3.3V power supplies |
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Shallow trench isolation |
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Dual gate oxide |
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Surface channel NMOS and PMOS |
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Cobalt silicided source, drain and gate |
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Borderless contact and vias |
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High density plasma gap fill |
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FSG inter-metal dielectric |
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Native transistors |
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Metal-Insulator-Metal Capacitor ( 1fF/µm2 or 2fF/µm2 ) |
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Thick metal spiral inductor |
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Varactor Metal Finger Capacitor ( 1.30 fF/µm2 ) |
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Thick Metal Spiral Inductor ( 2.3µm ) |
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Ft NMOS ( 56.2 GHz ) | |
Physical Design Rule
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Electrical Design Rule (Specification)
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