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CMOS 130nm FaStack (3D-IC Integration)定价

CMOS 130nm FaStack(R)

TECHNOLOGY:

CMOS 130nm FaStack (3D-IC Integration)

Met. layer(s):

6 per Tier (Metal 6 is used as bond interface) + TSV (Through Silicon Via)

Poly layer(s):

1

Maximum die size:

2cm x 2cm

Usable cells:

535 digital cells in both Low Power Low VT and Low Power Std VT

Available I/O:

I/O cell library with digital pads is available for 1.2V/1.5V core 3.3V I/O, 5.0V Tolerant

Temp. range:

-40° C. / +125° C.

Supply voltage:

1.2V/1.5V core 3.3V I/O, 5.0V Tolerant

 

SPECIAL FEATURES:

High performance mixed analog/digital process. Two Tiers bonded face-to-face

 

 

APPLICATION AREA:

Mixed Signals analog/digital, Pixels Arrays, Large Digital Designs, System on Chip

 

 

LIBRARIES:

 

Digital cells:

All the standard digital cells plus composed cells (complex gates, arithmetic cells, register files,...).

 

 

Megacells:

Single Port RAM, Double Port RAM, ROM.

RAM/DP-RAM/ROM:

Memory Compilers.

 

 

DESIGN KITS:

 

Unix based:

CADENCE, SYNOPSYS, MENTOR, MicroMagic

Windows based:

none

 

 

PACKAGING:

All standard packages (DIL, LCC, PGA,...).

 

 

TEST:

Contact CMP

 

 

INTERFACE FORMAT:

GDSII, CADENCE

 

 

SPICE parameters:

SPECTRE, HSPICE, ELDO

 

 

DRC, ERC rule set:

Calibre DRC/LVS/3DLVS/PEX, Assura LVS/QRC, Hercules

 

 

DESIGN SUPPORT:

DRC checking (free for submitted designs)

 

 

PRICES:

 

Cell libraries:

Distributed under NDA

Design kits:

Distributed under NDA

Prototyping:

See the general CMP price list for prototyping

Low volume production:

Depends on each specific case; contact CMP

 

 

TURNAROUND TIME:

 

Typical:

TBD

 

 

 

Tezzaron

3D-IC Integrated 2-tier stack 130nm CMOS

1800 Euro/mm2

 

 

 

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